Instructor:
Jiang B. Liu, jiangbo@bradley.edu
Professor of Computer Science &
Information Systems
Phone: (309) 677-2386
Prerequisites:
CS220 Computer Architectures
Lecture:
3:00pm-4:15 pm, Tue, Thurs. at BR
180
Office
Hours:
2:30-4:30pm Mon, Wed; 1:30-3:00pm
Tue, Thurs. at BR 177
or by appointment.
This is a graduate course in computer architecture for
computer science and computer information systems majors and minors. The goals
of the course are to provide students with a foundation of advanced computer
architecture, both tightly coupled parallel models and distributed parallel
models. Focus is on implementation issues and parallelization of algorithmic
tasks.
|
Unit 1 |
1. Fundamentals of Quantitative Design
& Analysis - Defining of Computer Architecture. - Trends in Technology. - Quantitative Principles of Computer Design. |
Ch. 1 |
|
Unit 2 |
2. Memory Hierarchy Design. - Memory Technology and Optimizations. - Virtual Memory and Virtual Machines. - The Design of Memory Hierarchies. - Memory Hierarchies in ARM Cortex-A8 and Intel
Core i7. |
Ch. 2 |
|
Unit 3 |
3. Instruction-Level Parallelism and Its
Exploitation. - Concepts and Challenges. - Advanced Branch Prediction. - Dynamic Scheduling. - Advanced Techniques for Instruction Delivery
and Speculation. |
Ch. 3 |
|
Unit 4 |
4. Data-Level Parallelism in Vector,
SIMD, and GPU Architectures. - Vector Architecture. - SIMD Architecture. - Graphics Processing Units. - Detecting and Enhancing Loop-Level
Parallelism. |
Ch 4 |
|
Unit 5 |
5. Thread-Level Parallelism. - Centralized Shared-Memory Architecture. - Performance of Symmetric Shared-Memory
Multiprocessors. - Distributed Shared-Memory and Directory-Based
Coherence. - Synchronization. |
Ch. 5 |
|
Unit 6 |
6. Warehouse-Scale Computers to Exploit
Request-Level and Data-Level Parallelism. - Programming Models and Workloads for
Warehouse-Scale Computers. - Computer Architecture of Warehouse-Scale
Computers. - Cloud Computing: The Return of Utility
Computing. |
Ch. 6 |
|
Unit 7 |
7. Domain Specific Architectures. - DSAs, Deep Neural Network. - Google’s Tensor Processing Unit, an Inference
Data Center Accelerator - Microsoft Catapult, a Flexible Data Centre
Accelerator - Pixel Visual Core, a Personal Mobile Device
Image Processing Unit - CPUs vs GPUs vs DNN Accelerators. |
Ch. 7 |
All
assignments are due in the class on the due day.
Later homework will have 10% subtracted from the score for every late day.
· Assignments: 30%
· Class Attendance: 10%
· Test01: 10%
· Test02; 10%
·
Final Exam: 40%
(Final date will be announced later)
(100-90 A; 89-80 B; 79-70 C; 69-60 D; below 60 F)
This class home page is also posted at
"http://hilltop.bradley.edu/~jiangbo/" and
will be used to post the assignments and other class information.
You are also encouraged email me about
your questions related to the course or share related information with the
class.